Burst read

[Cadez Borut RDHW <b.cadez@iskratel.si>]

Hi.

I'm working on a master pci core, which has two (rx and tx) FIFO's and is
working in a half-duplex mode. When master is doing a burst read on the pci,
the incoming data is immediately put into a receiver fifo, to achieve the
maximum speed. Because data is read from the fifo with a delay (optionally
with a different clock speed), data on the pci and data on the backend of
the core is not the same in the particular moment.
My question follows: How master knows when to stop the burst (deassert
frame#), if it is not receiving data "real-time"?
As I'm told, master does not know the ammount of data it will read in
advance (at the beginning of the transaction), but simply says: "ok, one
more and that's it" (frame# = 1) during the burst. Therefore a timer of some
kind is not an option. Is that correct? Am I missing something here?
If anybody can help me out, I would really appreciate.

Regards,
Borut Cadez


Borut Cadez, RDHW1
IskraTEL Ltd, Ljubljanska 24a, SI-4000 Kranj, Slovenia
Tel: +386 64 27 2533, Fax: +386 64 221 552
Email: b.cadez@iskratel.si, URL: www.iskratel.si