Target-Abort Question

["Calle, Jaime" <JC121128@exchange.SanDiegoCA.NCR.COM>]

> Hi there,
> 
> I have a question on the behavior of DEVSEL# on the cycle following target
> abort.
> 
> According to PCI 2.2, Section 3.3.3.2, for a target to signal
> Target-Abort, it must deassert DEVSEL# and assert STOP# at the same time.
> This is clear. However, since STOP# will be asserted for a minimum of 2
> cycles, there are no words in the PCI 2.2 specification about DEVSEL#
> after the first cycle it was deasserted. Figure 3-14 suggests that once
> DEVSEL# is deasserted, it should stay deasserted, but again, there are no
> words stating this.
> 
> Since STOP# will be asserted for a minimum of 2 cycles, is it OK if
> DEVSEL# is deasserted for the first STOP cycle (to indicate Target-Abort)
> but then assert it again for the second STOP cycle, and finally deassert
> STOP# and DEVSEL# together? Will the master receiving the Target-Abort get
> confused and recognize a RETRY on the cycle following the Target-Abort?
> (Assume no data is transferred before Target-Abort).
> 
> Thanks in advance for your response.
> 
> Jaime Calle
> NCR Corporation
>