RE: Violation PCI spec again

["O'Shea, David J" <david.j.oshea@intel.com>]

Maarten,

Actually, I was writing the below when I reviewed your
text.  I realized I was assuming that you control the
design of the CompactPCI system, when in fact this is
not stated.   Do you control the design of the CompactPCI
system or only the design of the add-in cards?

If you control only the design of the add-in cards, then
you have no way to design your problem away generally, 
whether you cheat or not, unless you design your cards
specifically for the CompactPCI system that you will be
using.   In that case, you can choose your interrupt 
assignment pins on your add-in card to meet your interrupt
sharing/non-sharing requirements.    If your add-in
board designs are intended for multiple different motherboards
in the long-term, you have no solution.

The problem is that the Slot connector IRQ pin assignments
to PIRQ signal traces on the motherboard are NOT fixed
by any formula.  The mother board manufacturer may do it
ANY way that they want to, and they all do different things
based on their own concerns and design goals.  Only the
subordinate PCI bridge devices(below the bridge) have a fixed PIRQ
to pin assignment system, as outlined by the PCI-to-PCI
bridge specification.   But even these devices do not have
a "final" known pin-to-PIRQ signal trace relationship
because the PCI-to-PCI bridge device itself does not
have one on the primary PCI bus.   E.g.  You can use
the P2P bridge formula to calculate the exact Slot-Pin
to most-superior P2P-bridge pin output.  But you cannot
use the formula to know how that final most-superior P2P-bridge
bridge pin is connected to a motherboard PIRQ signal trace.

Since the final bus 0 slots (or PCI-to-PCI bridge devices)
or the other onboard PCI devices on bus 0 do not have a 
pre-ordained (Slot or device)-pin to PIRQ relationship, 
you have no idea how they are shared.    

For instance, on one motherboard, they might use the 
typical baber-polling rotational layout.   On another,
they might use the reverse rotation, on yet another,
all of the PINA inputs might be wire or'ed together,
all the PINB's together, all of the pin C's together,
all of the PIND together, etc.   They might do the 
PinA's seperately for each slot, but wire or all the
rest.   It is totally up to the motherboard manufacturer.
What the motherboard manufacturer did is conveyed to
operating systems in two ways, via the offset 3C register
in the PCI device itself, and through a PIRQ routing 
table defined in the BIOS.  (There are more tables in
Multi-CPU systems).

So, you cannot know how you interrupt will be shared
by the system.  It is system board dependent.  So, you
are left with the choice of mapping your board and
determining its map, and then choosing your add-in board
design pin assignments correctly for this board, or not
trying at all.   If you do this, then when you switch
motherboards later, you pin assignments will no longer
give you the guarantees you had, unless the new motherboard
uses the exact same pin-to-PIRQ signal trace relationships
as the previous motherboard.

---------------------------------------

If you do control the design of the CompactPCI motherboard,
then you can achieve your goals by controlling the bus
0 device and slot and most-superior PCI-to-PCI bridge
device IRQ pin to PIRQ trace relationships to guarantee
your shared/not-shared needs.   If you don't control the
motherboard, then you can't get that guarantee, unless
you reverse engineer the assingments on that motherboard
(or backplane) and then choose your IRQ assingments accordingly.
But this would be specifically for that motherboard, and
would not likely work on the next.

If you don't control the motherboard/backplane, then you
can't do it generally, because the decisions are made in
the backplane.   You can only do it specifically paired
to the decisions already made in a particular backplane,
and even then, you have to have a backplane routing that
would allow for this.   (For instance, a backplane routing
that or'ed absolutely every PCI device pin A-D of each
device to a single PIRQ pin (every pin is wire or'ed) would
prevent you from designing any IRQ pin selection on your
add-in board that would fullfill your needs.

(You laugh, the "backplane" in many laptop docking stations
does exactly that.  All of the IRQ pins are wire or'ed together).

-David O'Shea