PCI Power Management Implementation Issue

[m.erber@avm.de]

Hello !

We are implementing a PCI 2.2 compliant PC add on card,
i.e. capable of using PCI Power Management features.

To support wake up from D3cold we detect the presence of Vaux on the PCI slot
and supply the boards core logic in D3cold with 3.3V Vaux when available.
The PCI interface chip I/O cells are connected to Vio PCI slot pins all the
time.

The question is, what happens with the PCI interface chips I/O cells when in
D3cold.

In all existing (today available) PCs the Voltage of the PCI slot Vio Pins is 5
Volt.
In D3cold State this voltage is switched off, as of the main 5V Vcc too.
Now only the core logic is running from Vaux.
Whats about uncontrollable leakage current from core to I/O cells to PCI slot,
vice versa ?
Are there any recommendations or known circuit tricks how to handle PCI IF chip
Vio pins ?

Thanks in advance for any help or advice,

     Matt.


Matthias Erber
AVM Berlin GmbH
m.erber@avm.de