Can devices generate RMW cycles in PCI 2.2 ?

["Scott C. Karlin" <scott@CS.Princeton.EDU>]

In PCI 2.2, can a master capable PCI expansion board generate a
read-modify-write bus cycle?  That is, can it generate an atomic
read then write burst?  If not, can the expansion board lock the
bus and then perform a read cycle followed by a write cycle?

My scenario has multiple slave CPUs which need semaphores to
gain access to shared resources.

It appears that the LOCK# signal would help.  However, the
description on page 11 and in appendix F leads me to believe
that in version 2.2 of the PCI specification this is just not
possible.  Is this correct?

Thanks,
Scott

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Scott C. Karlin                             Princeton University
Graduate Student                            Department of Computer Science
Voice: (609) 258-5386                       35 Olden Street
Email: scott@cs.princeton.edu               Princeton, NJ 08544-2087
WWW:   http://www.cs.princeton.edu/~scott
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