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Re: cacheline



> 
> Hi
> can anybody brief about cacheline.

Briefly:

As a bus master, if you issue a Memory Write & Invalidate, then you must
intend to write exactly an integer multiple of the cacheline number of
bytes.

ie: if the cacheline is set to 32 bytes, then you can issue MWI only
for 32, 64, 96, 128, etc... bytes.  If you intend to write any other
number of bytes, you must not use MWI.

> Thanks in advance
> kumar

-Richard Walter
rwalter@corp.auspex.com
Note: I speak for myself, not for Auspex.