RE: cacheline

["Solomon, Gary" <gary.solomon@intel.com>]

The idea behind the MWI instruction (and hence the need to keep the cache
line size info available) is to enable better host, and memory bus
throughput by eliminating any potential cache write back traffic to memory.
By guaranteeing that the transaction will neatly replace entire numbers of
cache lines, the host CPU(s) simply invalidate the associated line (if the
line were currently cached on chip)

Regards,
Gary Solomon - Intel

-----Original Message-----
From: Richard Walter [mailto:rwalter@corp.auspex.com]
Sent: Tuesday, February 15, 2000 1:28 PM
To: pci-sig@znyx.com; kskumar@chiplogic.com
Subject: Re: cacheline


> 
> Hi
> can anybody brief about cacheline.

Briefly:

As a bus master, if you issue a Memory Write & Invalidate, then you must
intend to write exactly an integer multiple of the cacheline number of
bytes.

ie: if the cacheline is set to 32 bytes, then you can issue MWI only
for 32, 64, 96, 128, etc... bytes.  If you intend to write any other
number of bytes, you must not use MWI.

> Thanks in advance
> kumar

-Richard Walter
rwalter@corp.auspex.com
Note: I speak for myself, not for Auspex.