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Bus Master Write Problems
We have implemented several PCI expansion cards based on the AMCC 5933
interface chips. We have successfully implemented high-speed frame grabbers
that input parallel data to the host PC at over 35 MB/sec. Our problem is
that we are not able to do this consistently in various computer systems.
For reference, all of our work uses NT device drivers.
Our initial development baseline was the Dell XPS H and D series 266MHz
Pentium II system. These worked fine. The boards appeared to work fine in
a Compaq 450MHz PII AP500 workstation also. When we purchased a Dell 450
MHz PIII system (XPS T series), we started to have FIFO overflows (add-on
FIFO's not the 5933 FIFO's) because there were long gaps in time where the
PCI bus would not acknowledge our card's bus master request. We turned off
Legacy USB Support in the BIOS and increased the add-on FIFO size to 16K
words, and we are now able to handle the ~700 usec periods when our bus
master requests are not honored.
Now we have purchased some Compaq AP550 workstations based on the new Intel
840 chipset Coppermine 733 MHz PIII motherboard. These systems seem to not
honor bus master requests for up to 3 msec at a time. We cannot easily
bridge this interruption with our add-on FIFO's. Any suggestions? What can
we do to stop having to tune/redesign for every new motherboard?
Terry S. Duncan
Computer Systems Manager
(505) 846-6783 voice
(505) 853-7243 pager 7103
(505) 846-2213 fax
3550 Aberdeen Ave SE
Kirtland AFB, NM 87117