PCI Master Conflict

["ANCUD ANCUD" <ancud@ru.ru>]

Hello,
 
We have implemented  PCI expansion card. While testing this
board on   Personal Computer "Pentium 166MHz" (ChipSet
2371AB) under OS "Windows_98"  a conflict occurred
sometimes. That is like this:
	The PCI interface controller of our board  as Master (let
us call it as Master_1) intends to complete single Memory
Write transaction. When the signal GNT# of Master_1 is
asserted,  "Master_1"  begins the transaction. A Target
device  asserts the signal "DEVSEL#"  and "Master_1"  waits
for assertion of "TRDY#".
A "STRANGE" Master sometimes begins its transactions. It
happens within 32 clocks beginning from assertion of
"FRAME#" and if the parameter “DMA” for the PC
hard disk is set ( setting of the parameter DMA was
performed by choosing the following Windows menu way -
Control Panel/System/Device manager/Disk drivers/Generic IDE
Disk type47/Property settings).

After that, the PC comes into the following “Hang
up” state :
1. "Master_1 " considers that the last transaction has been
correctly completed and continues its operation. 
2.	A device is trying to perform write transaction on the
PCI bus (address=0020h,  C/BE[3..0]=0011, data=064h).  But
the transaction ends by assertion of “STOP”
without “TRDY”. This sequence is  being repeated
.

Why does  a “Strange” Master  start a new
transaction cycle while the “Master_1” has not
yet completed its transaction cycle and so the bus has  not
yet come in the IDLE state (when IRDY is asserted)?
Any help with this question is much appreciated !!!

Thanks,

Aleksey Ryzhov 
Hardware engineer
Ancud@ru.ru
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