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How to Model Test Load in synopsys

 Hi 
  I want to know how can we model 
            Test Load conditions for OUTPUT buffers for Tval(min,max)
Rising/Falling Edge
  as described in 
     
     PCI-X Revision 1.0 

     Figure 9-8,9-9,9-10
     page 189 

     Figure 9-11
     page 190

  for synopsys synthesis tool.


Thanx in advance for your response

Best Reagrds
Sanjay Goyal