We are currently facing some problems while supporting io cycles in our pci target corecell.
There is an ambiguity in pci specs. and the compliance checklist regarding bursting to io space.
The PCI specs. Rev 2.2 ( Clause 3.2) clears mentions that bursts are supported in both memory and I/O space.
The PCI Compliance Checklist Rev 2.2 (Clause 2.4) contradicts the above statement. The clause deals with target reception of i/o cycles with legal and illegal byte enables. It states that for a single i/o cycle with valid be encoding, the target should end the transfer with a disconnect.
Also, the address and BE encoding is meant only for the first dataphase in an IO cycle. So, in case a IO bursting is supported, are all byte enables valid for subsequent data transfers ?
Can someone guide us on this matter ?
CG-CoreEL Logic Systems Ltd.
Pune -411 005
Tel : +91-20-5533982,5538074