> The way it works is that FPGA pads can be configured to support > many different signaling standards. This is not true for 9 out of 10 FPGA/CPLD's which claim PCI compliance. Most of these have a single output mode (3.3 volt) and no clamp diode. In small print there is often a disclaimer something like "outputs are PCI electrical specification compatible (no internal clamp diode)" -- Stuart