[Q ] A synthesis problem with PCI constraint

[Yang Li <yang_li1@yahoo.co.uk>]

I have a design which is to be targeted to ASIC.

This design has been synthesized with 66 Mhz PCI
constraint. Timings are not met with a slack of approx
-4 ns
I gave worst case constraints from PCI side. 

As the code changes will take a lot time again to
simulate, I have another quick option
I am sure that this design will work on 33 Mhz clock.

Now what method I am following is 
1) Synthesis with 66 Mhz constraint with worst case
PCI delays. Let the logic be generated with max
efforts.
2) Generate timing reports for 66 Mhz , 33 Mhz . (
Ofcource 66 mhz will fail. )
3) Target it to ASIC. with a facility on board made
for 33 Mhz, 66 Mhz. ( M66EN and Config space bit to be
tied from board jumpers ).
4) Assume that PCI chipset will give me best timings (
If I put the card nearer to chipset ), I will give a
try on 66 Mhz enable via board jumpers.


Is this method appropriate ? What I am assuming is bus
will not give me worst timings.


Thanks in advance 

Yang Li 




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