RE: pci compliant devices?

["Ingraham, Andrew" <Andrew.Ingraham@compaq.com>]

> What I don't understand is how FPGA/CPLD's claim
> both PCI compliance as well as TTL, LVTTL, LVCMOS 
> compliance. PCI is reflected wave switched with the
> CLK->Q time (Tval) spec being the time from the 
> clock edge to Vstep/Vtest.
> 
> This in contrast to TTL, LVTTL, LVCMOS in which 
> CLK->Q is the time from the clock edge to the output
> reaching Voh min or Vol max.

But this is only a difference in how you use, or look at, the driven
outputs.

There is nothing preventing you from designing one CMOS output, and
measuring it with different test loads and/or voltage levels.

I can measure a TTL or a CMOS chip's output with a 10pF load or a 50pF load
or 250pF load, or even a 100ohm pull-up resistor.  I will get different
timings.  That doesn't mean I have to use four different part numbers and
treat it like four different chips; they are all the same chip.

PCI is basically CMOS.  PCI's 5V environment voltages (Vil(max), Voh(min),
etc.) look just like TTL.

Regards,
Andy