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Re: parity check and data phases w/o transfers

Before answering your questions, I have to clarify the
parity checking versus parity error reporting.

For the checking, the checking of PAR as soon as the valid
data sourced on the bus by indication from the xRDY#.

If i read the spec., one can free to check the correctness of
the parity @ every data phase, however, you only REPORT
the error via PERR# when the data phase is completed. (see p.12 in
the spec. 2.1 section 2.2.5)


----- Original Message ----- 
From: Tom Keaveny <tak@core.rose.hp.com>
To: <pci-sig@znyx.com>
Cc: <tak@core.rose.hp.com>
Sent: Friday, March 10, 2000 10:24 AM
Subject: parity check and data phases w/o transfers

> Greetings,
> According to the 2.1 spec, PAR should become 
> and remain valid during data phases once the data first
> becomes valid (signified by the initial assertion of TRDY#
> or IRDY#, depending upon who is sourcing data).
>         Some basic questions are:
>             - when does parity checking begin?
>           (e.g., at first assertion of the sourcing xRDY# ?)
> - does checking occur on every data phase?
>   (independent of whether data was actually transferred)
> The spec is somewhat vague in this area...
> ==
> tom keaveny
> agilent technologies
> tom_keaveny@agilent.com