RE: FIFO sizes

[Duncan Terry S Civ AFRL/DES <Terry.Duncan@plk.af.mil>]

Tom,

We have had experiences where 4Kx16bit FIFO's were not sufficient.  Other
bus activity blocked access for up to a msec or two.  Normally, this
activity can be overridden by the bus master, but there can be other issues
with that (i.e. overall system performance and you mention a heavily loaded
system).  We are not a commercial organization and we build small numbers of
boards (30-40) so we have started using 16Kx16bit FIFO's for robustness.

One caveat is that our goal is to get throughput rates as close to 80 MB/sec
as possible.  As this is six times faster than your desired rate, 2-4K
FIFO's may provide the same margin for you that the 16K FIFO's provide for
us.

Terry S. Duncan
duncant@plk.af.mil
(505) 846-6783 voice
(505) 853-7243 pager 7103
(505) 846-2213 fax


-----Original Message-----
From: Tom Verbeure [mailto:tom.verbeure@mie.alcatel.be]
Sent: Tuesday, March 14, 2000 4:43 AM
To: pci-sig@znyx.com
Subject: FIFO sizes



Hello All,

I was wondering whether there are certain rules of thumb regarding the
sizing of transmit/receive FIFO's for master operations.
For our current application, we will need an average transfer rate of
roughly 15 Mbytes/s, but this can arrive in bursts. What is the maximum
time that we should buffer our data before we will get a grant from the
PCI arbiter? (On a heavily loaded PC)
Assuming that this time is 100 us, a buffer of 1500 bytes should be
sufficient. Let's take 2k byte  to have some more margin. Is this a
reasonble size that will avoid dropped data?

Thank you,

Tom Verbeure
Design Engineer
Alcatel Microelectronics