Re: FIFO sizes

[Rick Collins - Arius <PCImail@arius.com>]

I worked on a PCI data capture card which was transfering data to/from a
RAID disk controller. We needed a 25 MB/s transfer rate. Since the size of
a memory chip has little impact on the cost until you reach the top end, we
used a pair of 4M x 16 bit SDRAM chips and made a 4 block, ping pong buffer
of it. We also used a small FIFO (48 words) inside the FPGA controlling
things. The data to/from the external interface was transferred at a
constant rate and the data to/from the disk drive was in bursts as
determined by the RAID controller. 

Once we got the FIFO size adjusted to the burst size, things worked well.
If the FIFO filled up before a PCI burst was done, we could interrupt the
burst and let it retry after we had empted the FIFO. 

I believe this design was tested at up to 30 MB/s and could have worked at
higher rates if the RAID controller had been tweeked. 

So you might want to consider dumping the FIFO chips and going with an
SDRAM controlled by a PLD or FPGA. That way you can get up to 500 ms of
data buffering for a low cost. 


At 10:32 AM 3/14/00 , you wrote:
>Hi Tom,
>
>	For the system we are building we are using 256K word buffer for 16 MB/sec 
>data rate.  Reason is that, we want to handle up to 15 ms for any unexpected 
>delays in Master operation & any unexpected seek time on hard disk & to 
>allow op sys to handle interrupt process current data setup for next 
>transfer etc.  Since we need to run continously for several hours, with no 
>data loss, we choose this size.
>
>We tried with 4 kB fifo and see that, we fill it up quite often before we 
>start reading.
>
>>Hello All,
>>
>>I was wondering whether there are certain rules of thumb regarding the
>>sizing of transmit/receive FIFO's for master operations.
>>For our current application, we will need an average transfer rate of
>>roughly 15 Mbytes/s, but this can arrive in bursts. What is the maximum
>>time that we should buffer our data before we will get a grant from the
>>PCI arbiter? (On a heavily loaded PC)
>>Assuming that this time is 100 us, a buffer of 1500 bytes should be
>>sufficient. Let's take 2k byte  to have some more margin. Is this a
>>reasonble size that will avoid dropped data?
>>
>>Thank you,
>>
>>Tom Verbeure
>>Design Engineer
>>Alcatel Microelectronics
> 
>
>Ravi C. Kaipa     Ravi.Kaipa@GSFC.NASA.GOV
>Code 553.2  PH: 301-286-7012, Fax: 301-286-1672 
>Building 11, Room E-17
>NASA/Goddard Space Flight Center
>Greenbelt, MD 20771



Rick Collins

rick.collins@arius.com


Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design

Arius                         http://www.arius.com
4 King Ave                    301-682-7772 Voice
Frederick, MD 21701-3110      301-682-7666 FAX