RE: FIFO sizes

[Tony Clark <Tony.Clark@mn.efi.com> (by way of Daniel Weaver <danw@znyx.com>)]

Tom, 

Several years ago we were forced to increase our fifo size from 32K to 128K
bytes to support a 40Mbyte continuous stream.  We found that one of the
tasking operations was to simply open a new DOS window.  In this case, the
PC will write each pixel to the new window over the PCI bus and was using
too much of the the bus bandwidth.  

Part of the problem was the some video drivers would start sending data to
the video card and when the small fifo on the video card was full, the PCI
retry mechanism was used to throttle the data, wasting lost of bus
bandwidth in the process.  Fortuneately most of the video drivers were
fixed and now use some from of software handshake to prevent wasting bus
bandwidth with continuous retry.  There is no requirement that other PCI
cards not use the retry mechanism in this manner, so watch out for killer
PCI cards.

The second thing that we found was that the intel chips 440BX, 820, 840
give priority to PCI writes from the processor.  When we run a test program
that does continuous writes to the PCI bus (much like a video driver
writing pixels) the available bus bandwidth will drop from 125 Mbytes/sec
to 7 Mbytes/sec with the 440BX chipset.  Current testing on 820 and 840
systems show that the available bandwidth drops to 12 and 10 Mbytes/sec
respectively.  In short, an application could cause any size fifo to be
insufficient.

The situation has improved since the addition of the AGP bus because the
video card (a major user of PCI writes) and has moved off of the PCI bus.
But the fact remains that you will be dependant on the other cards and
applicatons on the PC.  I think that you should be safe with a 32K byte
buffer for a 15 Mbyte/sec stream, but you will still have to watch out for
killer applications or PCI add-in cards and will need to test, test, test.

Tony Clark 

> -----Original Message----- 
> From: Tom Verbeure [tom.verbeure@mie.alcatel.be] 
> Sent: Tuesday, March 14, 2000 5:43 AM 
> To: pci-sig@znyx.com 
> Subject: FIFO sizes 
>  
>  
>  
> Hello All, 
>  
> I was wondering whether there are certain rules of thumb regarding the 
> sizing of transmit/receive FIFO's for master operations. 
> For our current application, we will need an average transfer rate of 
> roughly 15 Mbytes/s, but this can arrive in bursts. What is  
> the maximum 
> time that we should buffer our data before we will get a  
> grant from the 
> PCI arbiter? (On a heavily loaded PC) 
> Assuming that this time is 100 us, a buffer of 1500 bytes should be 
> sufficient. Let's take 2k byte  to have some more margin. Is this a 
> reasonble size that will avoid dropped data? 
>  
> Thank you, 
>  
> Tom Verbeure 
> Design Engineer 
> Alcatel Microelectronics 
>  
>  
>