RE: pci compliant devices?

["Ingraham, Andrew" <Andrew.Ingraham@compaq.com>]

>> But this is only a difference in how you use, or look at, the driven
>> outputs.
>> 
>> There is nothing preventing you from designing one CMOS output, and
>> measuring it with different test loads and/or voltage levels.
>
> But the difference between incident and reflected wave signaling is 
> a function of the driver, correct ???

No.  Well, only partly.  Incident/reflected wave switching describes how the
signal electrically behaves once it's on the board traces.  Which one you
get (and there is a lot of overlap) does depend on the driver's drive
strength, relative to the characteristic impedance of your board traces and
how you've routed your signals.

You can take a strong driver (which could drive lines with incident wave
signaling) and put it in the middle of a lower impedance trace, and ...
voila ... you get reflected wave switching.

You can take a weaker driver (intended for reflected wave switching) and put
it on one end of a single higher impedance trace, and get incident wave
switching.

Reflected wave switching isn't new to PCI.  It's been used for decades
(CMOS, TTL).  ECL was designed for incident wave switching, when properly
used; and the same may be true of the stronger CMOS/TTL types (48-64mA
outputs), but much ordinary CMOS and TTL had reflected wave switching going
on.

Incident vs. reflected wave switching isn't something you design into the
driver, like 3-state vs. open-drain.  What you have is a broad spectrum
between weaker and stronger drive strengths, and one end primarily does
reflected wave switching while the other end mainly does incident wave
switching, BUT depending on the actual traces and loads.

> What I am trying to understand is say I have a CPLD with a one size
> fits all (PCI, TTL, etc. compliant) output driver. It's CLK->Q spec 
> guarantees that the outputs will be driven all the way to the 
> rail within 15 ns.

"All the way to the rail" is an interesting way to spec it.  Driving a test
load, many drivers would asymptotically approach but may never get all the
way to the rail.

>Now will this device meet the PCI setup requirements of 7 ns
> in spite of the fact that it does not meet the PCI spec for CLK->Q
requirement
> of 11 ns ???

If it doesn't meet the PCI spec's Tval limit of 11 ns, using the PCI spec's
measurement criteria (test loads and measurement thresholds), then it
doesn't comply with PCI, plain and simple.  No need to go further.

If the 15 ns wasn't measured with PCI test loads and thresholds, then it
doesn't tell you anything.

>It should since it is not relying on the 10 ns reflected wave 
> prop time in order to reach the required high or low voltage.

Where did it say that it doesn't use reflected wave switching?  I must have
missed that.

Unless it is a rather strong driver (which probably puts it out of class for
PCI use), it will get reflected wave switching when the trace impedances are
low and the loading is heavy, and the IC was one that came out of the "oven"
at the weak end of the processing range, and at high temperatures, etc.

BTW, a "5 volt" PCI I/O is perfectly suitable as a TTL compatible I/O, since
the 5 volt PCI specs are derived from those ancient TTL electrical specs
that the industry had been using for years.  (But "TTL" encompasses a very
wide range of drive strengths.  As do "CMOS", "LVTTL", and "LVCMOS".  Those
designations primarily describe input/output voltages, not current
capabilities.)

Regards,
Andy