When I first looked at the PCI spec, and read the section you quote regarding the reflected-wave methodology, I had a difficult time understanding the specification's interpretation of transmission line theory. It turns out that the theory can be interpreted from many perspectives, and reading one paragraph will likely not suffice to resolve your question.
The short form of my answer to your question may seem to contradict the specification somewhat [or rather the specification has such a short answer that it can easily be misconstrued]. Here's my shot at it:
Driver "size" deals with current switching capability, which is proportional to the rate at which the driver will charge the signal path's C component. Thus, the bigger the driver, the faster the edge [slew rate] will be. The more "vertical" an edge gets, the closer to a square-wave, which means the harmonic content will be higher. Thus, the signal path is subjected to a proportionally higher frequency component [re: definition of a square wave].
The implications can be mathematically parsed again, from many different perspectives. For example, the rapid change [dI/dT] causes a proportionally rapid change in flux [i.e. EMF], to which the inductance of a load along the line will react.
Another example of "interpretation" is that "high speed signals" are not a problem because of their rate of repetition, but rather because of the speed of their edges [dV/dT]. A high frequency free-runing clock will have to have high-speed edges; but a single pulse in one hour of time has no frequency to speak of in terms of Hz, but if it has a fast edge speed, then it contains a high-frequency component [in terms of dV/dT].
Therefore, the reflection is an effect caused by the combined attributes of the signal path and the driver. However, the signal path's dominant attributes include resistive, inductive and capacitive components at every point along the path, which includes the termination at BOTH ends of the line. Yet the driver's only dominant attribute is the current-switching capability, which is directly proportional to it's size, but which is LIMITED by its impedance [Ohm's law].
This is why transmission line drivers have "series termination", in which a resistor matching the impedance of the transmission line is in series from the driver. In such a case, there exists a resistor network, in which a voltage divider is formed. WIth the two impedances are the same, the incident wave will only reach 50% of the rail, until the reflected wave reaches the driver -- at which point the impedance of the line is effectively infinite, thus the wave continues all the way up to the rail [causing the step-waveforms, in which the size of the step in terms of T is twice the length of the transmission line].
This is why I think the PCI specification's referring of a "sized" driver is unclear. It could imply current switching capability, but could also imply termination. Still worse, it leads the reader to believe that physical size of a driver is what limits the signal to "half the voltage", which is simply not true if there is a series resistance in the driver. In that regard, what Xilinx does in terms of one-size-fits-all is unimportant [as long as they can drive current through their own impedance, which is obviated].
So the real question [IMHO] is not what is the size of the driver, but rather what is its impedance?
Forgive me for assuming, but if you care to read more on the topic, may I recommend the Motorola MECL data book(s). They contain an excellent paper, primarily concerned with PCB layout and design constraints when dealing with high-speed signals. It deals with transmission lines [controlled-impedance signal paths], the effects of termination and sound clock distribution methodologies.
The paper is actually significantly abridged in the current editions [the first edition of the paper spaned 35-40 pages in the '70s, and I still have a copy for that reason].
I don't know if this helps -- I cannot answer for Xilinx, but I thought we should form the question more appropriately.
From: Stuart Adams [mailto:email@example.com]
Sent: Tuesday, March 14, 2000 2:52 P
To: Ingraham, Andrew
Subject: Re: pci compliant devices?
> But this is only a difference in how you use, or look at, the driven
> There is nothing preventing you from designing one CMOS output, and
> measuring it with different test loads and/or voltage levels.
But the difference between incident and reflected wave signaling is
a function of the driver, correct ???
From the PCI 2.1 spec section 4.1.2:
"... PCI is based on reflected wave rather than incident wave signaling.
This means that bus drivers are sized to only switch the bus half way
to the required high or low voltage. ..."
What I am trying to understand is say I have a CPLD with a one size
fits all (PCI, TTL, etc. compliant) output driver. It's CLK->Q spec
guarantees that the outputs will be driven all the way to the
rail within 15 ns. Now will this device meet the PCI setup requirements of 7 ns
in spite of the fact that it does not meet the PCI spec for CLK->Q requirement
of 11 ns ??? It should since it is not relying on the 10 ns reflected wave
prop time in order to reach the required high or low voltage.