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Re: FIFO sizes
Thanks everybody for the really usefull comments.
Since we are not using FPGA's, but designing an ASIC with on-chip RAM, we
cannot go for the really big FIFO size that have been suggested. Luckily, we do
not require a 100% overflow-proof solution for the 15 Mbytes/s. Our design also
contains a 2 Mbytes/s secondary data stream with somewhat higher reliability
requirements. I will certainly increase the FIFO size for that one.
"Zinaty, Amir" wrote:
> As you have specified, on the Intel 82559 we have a 3Kb Fifo for each
> These Fifo sizes are good enough for ALMOST all practical cases. However,
> there is a mechanism which can handle the cases of Fifo overflow. If you can
> tolerate an overflow from now an then (would be very rare), the 4Kb Fifo you
> have suggested could be a good choice.
> -----Original Message-----
> From: Tom Verbeure [mailto:firstname.lastname@example.org]
> Sent: Tuesday, March 14, 2000 3:36 PM
> To: Duncan Terry S Civ AFRL/DES
> Cc: email@example.com
> Subject: Re: FIFO sizes
> Meanwhile, I have been reading datasheets of some commerical chips on the
> market that have similar data-rate requirements.
> Eg. the Intel 82559 Fast Ethernet component has a seperate buffer of 3 K for
> receive and transmit, for a data rate of 100 Mbits/s = 12 Mbytes/s, so I
> a FIFO of 4 Kbytes should indeed be good enough.
> Duncan Terry S Civ AFRL/DES wrote:
> > Tom,
> > We have had experiences where 4Kx16bit FIFO's were not sufficient. Other
> > bus activity blocked access for up to a msec or two. Normally, this
> > activity can be overridden by the bus master, but there can be other
> > with that (i.e. overall system performance and you mention a heavily
> > system). We are not a commercial organization and we build small numbers
> > boards (30-40) so we have started using 16Kx16bit FIFO's for robustness.
> > One caveat is that our goal is to get throughput rates as close to 80
> > as possible. As this is six times faster than your desired rate, 2-4K
> > FIFO's may provide the same margin for you that the 16K FIFO's provide for
> > us.
> > Terry S. Duncan
> > firstname.lastname@example.org
> > (505) 846-6783 voice
> > (505) 853-7243 pager 7103
> > (505) 846-2213 fax
> > -----Original Message-----
> > From: Tom Verbeure [mailto:email@example.com]
> > Sent: Tuesday, March 14, 2000 4:43 AM
> > To: firstname.lastname@example.org
> > Subject: FIFO sizes
> > Hello All,
> > I was wondering whether there are certain rules of thumb regarding the
> > sizing of transmit/receive FIFO's for master operations.
> > For our current application, we will need an average transfer rate of
> > roughly 15 Mbytes/s, but this can arrive in bursts. What is the maximum
> > time that we should buffer our data before we will get a grant from the
> > PCI arbiter? (On a heavily loaded PC)
> > Assuming that this time is 100 us, a buffer of 1500 bytes should be
> > sufficient. Let's take 2k byte to have some more margin. Is this a
> > reasonble size that will avoid dropped data?
> > Thank you,
> > Tom Verbeure
> > Design Engineer
> > Alcatel Microelectronics