Re: PCI card trace length - Possible new ECR?

["Jim McManus" <Jim.McManus@xilinx.com>]

Olaf Birkeland wrote:
[snip]
> > Mechanical: Not a really big issue for FPGA vendors provided the pinout
> > allows the trace length to be met. Some of the newer small packages
> > (e.g. FG256) might not be advisable for 64-bit slot card applications,
> > unless you go with the PCI-X spec of 2.75' for the 64 bit extensions.
> > The PCI spec allows only 2' for the 64-bit extensions. Larger packages
> > such as the BG432 don't have an issue in this area.
> >
> 
> Even though this is the wording of the specification, wouldn't the smaller
> package in practice be better. FPGA timings are specified regardless of
> package. Given the same FPGA die (like an XCV300E which is available in both
> FG256 and BG432), the signal path from the FPGA bonding pad to the PCI
> connector would be about the same. But in the case for BG432, ~0.5' more of
> that path is in the package/bond wire.

We have to guarantee the timing pin to pin. When we characterize our PCI
solutions in the lab, we check the paths pin to pin. 

In some cases trace length can be an issue. I've seen add-in boards fail
because the clock trace was not exactly 2.5 inches. The motherboard
vendors design with the 2" (64-bit extension) trace lengths in mind.
PCI-X MB vendors will have to take both PCI (2.0") and PCI-X (2.75")
into consideration. 
 
> >From a signal integrity standpoint, the FG256 solution will have a more
> uniform impedance, while the BG432 will have a impedance mismatch somewhere
> in the "middle" of the path (max 2' on PCB, ~0.5' in the package). The
> impedance mismatch with FG256 is occurring close to the path end, thus
> giving less problems.
> 
> The FG256 will additionally allow placing the *die* closer to the PCI card
> edge due to the smaller package surrounding it. Thus the FG256 will give a
> shorter path, and more homogenous impedance, from the PCI connector to the
> die pad. To me, this should be better...... Do we need a new ECN from your
> side to allow usage of the smaller package styles?

Hmmm, I'm thinking about it. The ECR would not be towards the packages,
but rather towards the trace length mismatch between PCI-X and PCI on
the 64-bit extensions. But we can't obsolete the millions of existing 5
V systems, so it would probably only apply to 3.3 V PCI add-in cards.
Since PCI-X motherboards will probably only be 3.3 V on the PCI-X slots,
this would fit. 

I'd like to hear what people think on this subject, as I'm sure there
are a lot of opinions about this. 


Jim McManus
Xilinx PCI Applications Engineer