ASIC Spins for 66MHz PCI

[Mike Dini <mdini@dinigroup.com>]

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 >ASICs have the same problem we did; this path has to be tuned to fall
 >exactly in this 3 ns window. It takes about three spins of the design to
 >achieve this. We did our three spins in a week or two; the ASICs
 >designers had to go back to the fab and respin the design, which can
 >take up to three months per spin. I haven't heard of anyone getting it
 >right on the first try.

The QuickLogic team got it right on the first try -- and we meet 75MHz
with 64-bits. Yes it is difficult.

Jim -- Please keep the 'marketing hype' off this discussion board.
This is a technical forum and I find blatantly false statements such
as this to be insulting. I might note that it takes an $350 part in
a -6 speed grade that cannot be procured today to get Virtex to do
66MHz on the PCI bus. And Virtex 'E' cannot be used in a +5V PCI signalling
  environment, making this family totally useless for PCI design.