RE: ASIC Spins for 66MHz PCI

[Reza Vahedi <reza@cognex.com>]

I don't recall reading the original e-mail but let me see if I understand
you correctly. First, you Claim that any PCI device that do not comply with
5V PCI signaling are totally useless. You may want to reread the PCI
specification. On page 224 of PCI 2.2, it is clearly stated that 66MHz PCI
planar segments MUST use the PCI 3.3V keyed connector. Therefore, 66 MHz PCI
planar segments accept either 3.3V or universal expansion boards; 5V
expansion boards are not supported!!! Second, you make claims pricing and
performance claims about Xilinx devices. Are you absolutely sure that Xilinx
devices don't meet 66MHz PCI timing? What is the use of 75MHz timing other
than in embedded designs?  How cheap are Quicklogic parts compared to
anybody else's? By the way, you don't have to answer any of these questions!

You are right about one thing, let's keep it technical  BUT don't be biased
towards one vendor!

> -----Original Message-----
> From:	Mike Dini [SMTP:mdini@dinigroup.com]
> Sent:	Friday, March 17, 2000 11:37 AM
> To:	pci-sig@znyx.com
> Subject:	ASIC Spins for 66MHz PCI
> 
> ... deleted ...
> 
>  >ASICs have the same problem we did; this path has to be tuned to fall
>  >exactly in this 3 ns window. It takes about three spins of the design to
>  >achieve this. We did our three spins in a week or two; the ASICs
>  >designers had to go back to the fab and respin the design, which can
>  >take up to three months per spin. I haven't heard of anyone getting it
>  >right on the first try.
> 
> The QuickLogic team got it right on the first try -- and we meet 75MHz
> with 64-bits. Yes it is difficult.
> 
> Jim -- Please keep the 'marketing hype' off this discussion board.
> This is a technical forum and I find blatantly false statements such
> as this to be insulting. I might note that it takes an $350 part in
> a -6 speed grade that cannot be procured today to get Virtex to do
> 66MHz on the PCI bus. And Virtex 'E' cannot be used in a +5V PCI
> signalling
>   environment, making this family totally useless for PCI design.