66 MHz timing parameters

["Dror L." <drorl1@hotmail.com>]

Hello,

According to the spec the Tval time (CLK to Signal Valid Delay bused 
signals) is measured with the load circuit shown in Figures 7-6 and 7-7, 
which means 10pF.

Is this value used only for compliance check? Is it true for practice 
system? or in other words, which value should we use during the synthesis?

Thanks in advance,
Dror
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