Master enable Command bit

[Hugh Tarver <hwt@transtech-dsp.com>]

Hi,
I am using a PCI ASIC core on which the local bus (processor) cannot get 
access to the configuration space of the bridge except through a PCI 
loopback (configuration cycle being mastered and targetted by the same 
bridge).
For most applications that the board will be used in this isn't a problem. 
 However, for an embedded system, the local processor on the board will be 
the system master, and will have to configure the system.  This is 
impossible without setting the bus master bit in the configuration space 
COMMAND register.  Setting that bit is impossible from the local processor 
because of the necessity to master on the PCI bus to be able to access the 
configuration registers.
However, the bridge comes with an option (fixed as part of the 
configuration of the ASIC core) to have the bus master bit PERMANENTLY set 
to 1 (enabled).
Has anyone any ideas/experience on whether PC BIOSs or other system 
configuring devices will have any problems with finding a device with the 
bus master bit set after reset.  The PCI specification states that the bit 
should be 0 at reset.
Thankyou,
Hugh

Hugh W. Tarver
Transtech DSP
Manor Courtyard,
Hughenden Avenue,
High Wycombe,
Bucks.
England.
HP13 5RE