RE: Some basic queries

["Ingraham, Andrew" <Andrew.Ingraham@compaq.com>]

> 1. Unlike AGP, PCI uses only rising edge of clock for all its operations.
> Why PCI can't operate on both the edges of clock, what is the limitation
> factor?
> 
It is not necessarily a limiting factor.  Often the main limit is how fast
you can make the bussed signals reliably switch and settle at all devices.
Then you run the clock at the appropriate speed.  If PCI used both edges of
clock, then the clock would be 16.7 MHz rather than 33 MHz.  Running the
clock at 33 MHz is easy; getting the bussed signals to switch that fast and
meet all the timing requirements, is the hard part.

Using both clock edges adds some extra timing variations, such as
cycle-to-cycle jitter.  And it is more complex.

AGP, like PCI, uses only the rising edge of the CLK.  Only its source
synchronous Strobes are double edge triggered.

> 4. Tval timings of PCI-X 66 Mhz and PCI-X 133 Mhz are same, i.e 3.8 ns
> whereas PCI 33 Mhz and 66 Mhz have different Tval ( 11 ns and 6 ns
> respectively ). Why?
> 
Because.  (Sorry!)

33 MHz PCI came first.  Then a few years later, came 66 MHz PCI, and the
timing had to be trimmed a lot to make it possible.  Then came both 133 MHz
and 66 MHz PCI-X, which further trimmed Tval.

66 MHz PCI-X is a special case of PCI-X that is limited to 66.7 MHz.  It is
advantageous in systems where the bus settling times are longer, for example
if the system has more expansion cards.  You trade off clock speed for
number of expansion slots.

These timings were probably chosen based in part on information from
semiconductor vendors as to what they felt was possible to achieve.  3.8 ns
for Tval may have been deemed achievable and appropriate for both PCI-X
speeds.

> 5. If a system is operating at 33 Mhz, it is not guaranteed that clock
> will be stable at 33 Mhz, whereas once the frequency is 66/133 Mhz as
> would be in PCI-X, clock frequency will be constant. Why is this
> constraint with 33 Mhz operation?
> 
Again, 33 MHz PCI came first, and the only restriction was on its maximum
clock frequency.

At faster clock speeds, 66 MHz and above, it is more likely that a PLL
(phase locked loop) might be used in the clock circuits of each PCI or PCI-X
device.  PLLs don't tolerate sudden frequency changes without a time to
recover.  Hence the additional restrictions on clock frequency changes for
PCI-X or 66 MHz PCI.

Regards,
Andy