RE: Routing & Layout near PCI connector

["Ingraham, Andrew" <Andrew.Ingraham@compaq.com>]

> Another possibility I was thinking of was to establish a small Ground
plane
> on Inner layer 2 (it would just barely cover the 3.3V island) and place
the
> layers as follows:
>
> Component
> Ground
> Inner 1
> Power
> Inner 2
> Solder
 
That would give you an asymmetrical layer structure, which can cause boards
to warp or have other problems.  Discuss this with the folks who make your
boards.

When you must have signals that cross a plane split, placing caps across the
split does help, even if it's not ideal.  Better to route the signals so
they don't cross it, or shape the 3.3V island to help minimize crossings.

Regards,
Andy