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MSI Support, Ordering Rules

Hi all,

I just have a query about the MSI support in a core that handles more than one transaction. If i have to initiate a Mem Write DWORD (for a interrupt from local interface, MSI Support), then what are the Ordering Rules for that. Can it pass Posted Mem Write or DRR and DRC's. I am not able to find the ordering rules for this cycle in the specs.

Thanks,

Amit Shah
Design Engr,
DCM Technologies,
Austin, USA.