Memory Read Line and Memory Read Multiple

[jukka.alve@nokia.com]

Hello PCI experts,

Can anybody shed some light on the usage of the PCI commands
Memory Read Line and Memory Read Multiple? 

If a master (i.e. initiator) on a PCI expansion board 
uses one of these commands to read motherboard memory in 
long bursts, does it need to know something about the structure 
of the cache on the other side of the bridge? If the Memory Read Line 
command is used, is it illegal to try to read past the cacheline
boundary? How about with Memory Read Multiple, what if the
master decides to terminate the transfer before the cacheline
boundary is reached? Is this illegal? If not, what is the 
purpose of the distinction between these commands? 
How does the behaviour of a master that uses one of these
commands differ from one that uses the ordinary Memory Read
command?

Best regards,

Jukka Alve

jukka.alve@nokia.com