RE: Memory Read Line and Memory Read Multiple

["mano, oren" <mano_oren@emc.com>]

Hi ,
 
This is not what the spec says.
 
The target does not need to know what the cash line size is. And the master
can read any number of words when using MRL/MRM. The only command that force
full cache line transfers is MWI. A master may chose to implement MRL/MRM
without implementing the cacheline register.
 
 
Oren
 
 -----Original Message-----
From: Praveen.Durga@dcmds.co.in [mailto:Praveen.Durga@dcmds.co.in]
Sent: Tuesday, April 04, 2000 1:48 PM
To: pci-sig@znyx.com; jukka.alve@nokia.com
Subject: RE: Memory Read Line and Memory Read Multiple



hi 
th MRL and MRM bus commands r for increasing bus perfomance in case of burst
cycle. the only constraint in : 
MRL is : master has to start cycle with address and byte enables such that
reading till cacheline shouldnt be a problem, as master wants to read till
cacheline.(giving stress on the point that it is illegal to read upto
between any two cacheline boundary using MRL/MRM)

for target, it shud not give disconnect before cacheline size i.e buffer
pipelines shud keep pumping data till cachelinesize.

MRM is : this bus command is for reading multiple cachelines. target can
give disconnects at cachesize only. 
i hope i was on right track and u can work out with that...do get back if
any problem... 
regards 

Praveen Durga 
ASIC Design Engineer 
DCM Technologies INDIA 
Phone : 91-11-5719967 
             Extn    : 216/286 (O) 
http://www.dcmtech.com <http://www.dcmtech.com>  
Email : pdurga@mailcity.com 

	---------- 
From:   jukka.alve@nokia.com[SMTP:jukka.alve@nokia.com] 
Sent:   Monday, April 03, 2000 7:09 PM 
To:     pci-sig@znyx.com 
Subject:        Memory Read Line and Memory Read Multiple 

	Hello PCI experts, 

	1. Can anybody shed some light on the usage of the PCI commands 
Memory Read Line and Memory Read Multiple? 

	2. If a master (i.e. initiator) on a PCI expansion board 
uses one of these commands to read motherboard memory in 
long bursts, does it need to know something about the structure 
of the cache on the other side of the bridge? 

	3. If the Memory Read Line 
command is used, is it illegal to try to read past the cacheline 
boundary? 

	4. How about with Memory Read Multiple, what if the 
master decides to terminate the transfer before the cacheline 
boundary is reached? Is this illegal? If not, what is the 
purpose of the distinction between these commands? 

	5. How does the behaviour of a master that uses one of these 
commands differ from one that uses the ordinary Memory Read 
command? 

	Best regards, 

	Jukka Alve 

	jukka.alve@nokia.com