Re: Memory Read Line and Memory Read Multiple

[Manfred Kuhland <man@atlantek.com.au>]

Hi,
The Memory Read (MR), MRL and MRM commands have implications on
the behaviour of the target and define how much prefetching of data the
target
can do before terminating the internal access cycle.

If no side effects exist by prefetching data from the internal resource,
target
controllers are free to perform prefetching for any read command (MR, MRL

or MRM). This is recommended for any memory based targets because it
improves PCIbus performance.

However, if prefetching of data causes side effects (i.e. reading from a
streaming device such as a FIFO) the target is not allowed to prefetch
any
more words from the FIFO than what's indicated by the command type.

The MR cycle does not allow any prefetching by the target controller,
which
results in slow PCIbus cycles (single cycles or bursts) because the
target performs
only single cycle accesses to the internal resource. MRL provides for
internal
prefetching of data to the end of the cache line. The MRM command allows
prefetching beyond the cache line boundary which may improve PCI and
target
performance. In this case targets continue to prefetch data as long as
the FRAME#
signal from the master is active. The amount of prefetched data is only
limited by
the size of the target's tempory buffer.

The PCIbus specification does not enforce the master to read a complete
cache line even when the MRL or MRM commands are issued. Also, the
target is not required to service complete cache line reads either. Both
agents
are free to terminate a read access at any time.

If the master terminates an MRL or MRM cycle without reading to the end
of the
cache line boundary it has to know that the target data prefetching did
not cause
any side effects. Otherwise the unread data in the tempory buffer of the
target is lost.

Regards,

Manfred Kuhland
Director - Electronic Engineering
Atlantek Microsystems Pty Ltd
Innovation House, Technology Park,
Mawson Lakes, SA, 5095, AUSTRALIA

Tel:         +61-8-8260-8990
Fax:        +61-8-8349-4286
E-mail:    man@atlantek.com.au
Internet:  http://www.atlantek.com.au


jukka.alve@nokia.com wrote:

> Hello PCI experts,
>
> Can anybody shed some light on the usage of the PCI commands
> Memory Read Line and Memory Read Multiple?
>
> If a master (i.e. initiator) on a PCI expansion board
> uses one of these commands to read motherboard memory in
> long bursts, does it need to know something about the structure
> of the cache on the other side of the bridge? If the Memory Read Line
> command is used, is it illegal to try to read past the cacheline
> boundary? How about with Memory Read Multiple, what if the
> master decides to terminate the transfer before the cacheline
> boundary is reached? Is this illegal? If not, what is the
> purpose of the distinction between these commands?
> How does the behaviour of a master that uses one of these
> commands differ from one that uses the ordinary Memory Read
> command?
>
> Best regards,
>
> Jukka Alve
>
> jukka.alve@nokia.com