Address parity on PAR64 during SAC

[Shimon Rottenberg <shimon@mellanox.co.il>]

Hello,

I'm designing a 64-bit PCI target device.
According to PCI spec, all 64-bit targets qualify address
parity checking of PAR64 with REQ64#.
The spec also says that AD[63:32] and CBE#[7:4] are reserved
during the address phase of a single address phase transaction.

The question is:
Must a 64-bit target check for correct address parity on 
AD[63:32], CBE[7:4] and PAR64, for the address phase of a SAC
(Single Address Cycle)?
Is it required that the master drive correct address parity
for the high AD/CBE pins, although they are reserved during
a SAC?

Thanks in advance,
Shimon Rottenberg
Mellanox Technologies Ltd.
mailto:shimon@mellanox.co.il