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what happens if 2 INTs occur at same time
Hello PCI group,
first of all many thanks for the tips I got how to forward configurationcycles
over a bridge. It's fixed now. It wasn't a "software problem", we only had no
clock on the secondary bus. By the way, if someone uses the i21150 PPB, when
pulling the msk_in signal high we suppose that the p_clk signal will be also
high and not active. But they don't. Sometimes they become activity after power
up.
The thing why I'm writing is in general to ask about interrupthandling in CPCI
systems. We are not so close to a PCI-PC (interrupt) system, we only use the
CPCI bus to control several ATM modules. (The real traffic comes over a UTOPIA
bus.) The Host CPU is a 8240 from Motorola.
My question:
If we have more than 4 peripheral CPCI boards on a backplane, therefore two
board have to share one interruptline. What happens, when both assert the
interruptline before the interrupt acknowledge cycle comes thru the bus. I
remember by myself that there is no addressing mechanism whit this cycle. Which
board drives the vector onto the bus when two or more boards have driven the
interruptline ? Which spec. give some information about this toppic ?
Thanks in advance,
Jürgen Klemt
PS: When I search the spec. (PCI 2.2) with Acrobat Reaer for "interrupt", I
don't get all occurences of the word. Anyone else noticed something like that.
____________________________________________________________________
| |
| Hans-Jürgen Klemt |
| Design Engineer ADVA AG |
| (cellware broadband) |
| |
| Email jk@cellware.de Justus-von-Liebig Str. 7 |
| Tel (+49 30) 670 08 - 167 12489 Berlin |
| Fax (+49 30) 670 08 - 108 Germany |
| |
| WWW http://www.adva.de & http://www.cellware.de |
|____________________________________________________________________|