Memory Read/Write to Device

[Jens Richter <richter@nentec.de>]

Hi Cracks,

we are developing a System with an i960RM-CPU as master and 2 or more i82557 as
slaves.

Nowadays I try to unterstand how PCI acts in detasil.

My configuration-function (which detects devices on the second.
bus) works proper and I´ve setup my i82557-devices as follows:

BAR0 (memory mapped Registers) @ 0x50000000,

The CPU has an Secondary Outband Address Translation Window (SATU) @ 0x88000000.

So I think when I try to read from 0x88000000 this address will be translatet
as 0x50000000 on the secondary PCI-bus and I can read the CSR(Offset 0)
from the i82557.

But I receive a MasterAbort which means the target is not responding and
answering with DEVSEL.

Does anybody know the cause?

Any help appreciated.

Thanx in advance.

Jens Richter


-------------------------------------------------------->
Jens Richter              NENTEC Netzwerktechnologie GmbH
eMail: richter@nentec.de  Killisfeldstrasse 64
Phone: +49-721-9495-223   D-76227 Karlsruhe/Germany
Fax:   +49-721-9495-166   http://www.nentec.de