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AMCC S5933 and Master Abort
I have a question.
Under what circumstances will the S5933 Master Abort
bit be set (Interrupt Control Status Register, bit 20)?
My board is working correctly in an old
PC but not in a new one: I got Master Abort Interrupts.
The data sheet says:
> Master Abort. This bit signifies that an interrupt has been generated
> due to the S5933 encountering a Master Abort on the PCI bus. A master
> abort occurs when there is no target response to a PCI bus cycle. [...]
Is this related to the S5933 operation in slave mode? For master
mode, the Target Abort bit should be set (bit 21).
AFAIK, the 5933 is not operating in slave mode when this occurs.