RE: Any way to force a 64-bit transaction

["O'Shea, David J" <david.j.oshea@intel.com>]

Michael,

You can try using the MMX instructions:

MOVQ	memory, MMXreg

movq	dword ptr[edi], mm0  ; for example.  [edi] needs to be qword
aligned.

OR the SIMD instructions:

MOVAPS memory, SIMDreg

movaps dword ptr[edi], xmm0 ; for example. [edi] needs to be 16 byte
aligned.

You will probably have to code up the instructions
yourself using DB statements if you are using the
MS 6.11 assembler, since that assembler pre-dates
the instructions.  

Changing the caching mode in the device won't help.
Changing how the memory range is mapped in the CPU
also likely won't help.  (In theory it could, if you
marked that range as Write Back or Write Thru in the CPU cache,
it would put out a whole cacheline (64 bytes) on a write.  However,
the Front Side Bus to I/O Bus bridge may not be designed
to handle the transaction type that results.  Then again,
it might.  I would not try it myself).

Using the instructions above, you don't have to change
the memory caching attibutes in the processor.

NOTE:  I have not ever tried using MOVQ or MOVAPS
to access a slave PCI device.  But in theory it should
work.  

-David O'Shea


-----Original Message-----
From: Neal Palmer [mailto:neal@dinigroup.com]
Sent: Monday, May 01, 2000 9:10 AM
To: Michael Richardson
Cc: pci-sig@znyx.com
Subject: Re: Any way to force a 64-bit transaction



Michael,

We have had the same problem (same motherboard).  We can't get it to
assert Req64.  One solution is to use an Intel/DEC P2P 64-bit bridge.  It
will convert the 32-bit burst write into a 64-bit burst write (under
certain conditions).

Also, on this first set of 64/66 PCI chipsets, you are far better off if
you can manage to initiate DMA operations instead of using the CPU to push
data.  The next generation of chipsets might not have this "limitation".

-- Neal

On Fri, 28 Apr 2000, Michael Richardson wrote:

> 
>   We have a 64/66 card.
>   We are testing it against a Micron Samurai chipset motherboard with
> an Intel processor.
> 
>   We are looking for a way to *force* a 64-bit write from our (PIII) CPU
to
> our device so that we can test our handling of 64-bit operations. So far
> we have been unable to find a way to do this.
> 
>   Does anyone have any suggestions? Does it matter how we map the device?
> (Cacheable vs non-cachable) Are there any extra instructions on PIII that 
> might help us? Since it is really a 32-bit CPU with a 64-bit external bus,
> there is not (to my knowledge) a 64-bit write.
> 
>    :!mcr!:            |  Solidum Systems Corporation,
http://www.solidum.com
>    Michael Richardson |For a better connected world,where data flows
faster<tm>
>  Personal:
http://www.sandelman.ottawa.on.ca/People/Michael_Richardson/Bio.html
> 	mailto:mcr@sandelman.ottawa.on.ca	mailto:mcr@solidum.com
> 
> 
> 

-- Neal Palmer

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