Re: PCI system integration issues

["Peter Marek" <peter.marek@marekmicro.de>]

Ben,


the problems you observe be a problem of the pC chipset of the PC you are
using.
The issue here is that Northbridges have built in Puffers for processor to
DRAM and PCI master to DRAM accesses. On some chipsets, it seems to me, that
there is no coherency protocol for these buffers.
to make it clearer, let's do an example:

1) A PCI master writes data to main memory over the PCI bus.
2) The host bridge accepts the transfer and puts the data into internal FIFO
buffers before writing them to main memory to speed upt the PCI transfer.
3) At the end of the PCI burst, part of the data has been written to main
memory, and another part ís still in the FIfo buffers inside the chipset
4) The host processor now accesses the same memory location and wants to
fetch the data that has been written by the PCI bus master
5) The host bridge reads the data from main memory completelly and delivers
it to the processor. Because some of the PCI DMA data is still hanging
around in the Fifos, the processor partially gets stale data.

There are some more scenarios (Processor/PCI master read/writes) where Fifo
Buffers may cause incoherent data in a PCI system. It's rather tricky and in
practice the systems will fail sporadically unter varying processor/bus load
conditions.

Some chip set vendors have implemented the Fifo buffers very carefully,
others have not. Some BIOSes support to turn the buffers on and off, some do
not. Some chipsets flush the buffers under certain conditions. E.g. the
flush the PCI to DRAM write buffers when there is a PCI from DRAM read.

regards,

Peter Marek
General Director
MarekMicro GmbH
Kropfersrichter Str. 6-8
D-92237 Sulzbach-Rosenberg
Germany
Phone: 049 - 9661 - 908 - 210
Fax:      049 - 9661 - 908 - 100
----- Original Message -----
From: Ben Yurick <byurick@keithley.com>
To: 'PCI SIG email reflector' <pci-sig@znyx.com>
Sent: Thursday, May 04, 2000 7:53 PM
Subject: PCI system integration issues


>
> Hello, while we are on the AMCC topic, my company has a couple products
> that
> use the AMCC S5933QE PCI interface chip. We are experiencing very
> strange behavior
> with these products. One particular PCI card that uses the AMCC does bus
> mastering DMA
> from onboard hardware FIFOs to the PC's memory. This card fails
> busmastering at the device
> driver level occasionally. So far we can't make sense of this. I have
> replaced the AMCC with the
> 5935QF LSI and it did not help. What we see are failures in some
> operating systems and not others.
> For example, the card works fine in a Windows NT system with a 440BX
> chipset but it will _sometimes_
> fail in a windows 95 system with a via chipset. We have also seen
> fail/pass inconsistencies when moving
> it around on different PCI slots. We have several different device
> drivers to talk to the card as well. We also
> see variability there.. some device drivers will show busmastering
> failures others will run the card successfully
> forever. The system as a whole has me baffled. I examined the PCI
> busmaster transactions in the failing systems
> and see no PCI violations. The 5933/5935 always does transfers
> correctly. It will always do passthru transfers
> correctly also.
>
>     Is anyone aware of these kinds of system level issues with PCI
> devices with respect to the practically infinite
> combinations of PCI BIOS's, chipsets, operating systems, device drivers,
> etc? I would like to pin down
> what the offenders are so I know if we need to go redesign our card.
> There are many systems that our card
> runs flawlessly in so I hesitate. My company is setup so that our
> product get to run in many different computer combinations
> as our software drivers are developed. Almost every PCI product so far
> has some kind of a problem in certain
> systems and not others. It is frustrating because I dont know what to
> debug/fix if I cant pin down what is wrong and
> so far, there is no pattern as to what combinations do not play well
> together. I would like to say it is our design, but
> how can it work flawlessly in some systems? Also some of our design are
> so simple, it could really only be the 5933
> responsible and I cant blame that either!
>
> How can a software driver do busmastering successful sometimes and not
> others in same power cycle?
>
> How can Operating system be cause bus mastering failures sometimes and
> not others?
>
>
> Please anybody with some advice or suggestions please respond.
> I would be very thankful to anyone who could provide
> some insight! Thanks!
>
>
> Ben Yurick
> Design Engineer
> Keithley Instruments
> (440)498-2871