Re: RE: AMCC 5933

[paw <paw@ssec.wisc.edu>]

All,

I am hoping that the experts on our list can help with this.

- We are using AMCC's 5933 PCI controller for an appl.

- In regards to AMCC's "Add-On Bus" timing: there is a signal named
"PTADR#" that is used to signal to the controller to drive an address
onto the muxed address/data lines. I have not been able to find a spec
on this operation. e.g. "the address will show up on the DQ[] lines a
maximum of x nS after the falling edge of PTADR#"  Any help would be
greatly appreciated. Thanks.  --paw



Univ of Wisconsin
Space Science & Engineering Center
Republic of Madison, WI, USA