Dear paw, In the Spring '96 Databook (sorry I don't have one that's more current), it is on page 12-6 and 12-7, section 12.3.2, "Target S5933 Asynchronous Operation Register Access Timings" and corresponding figure 12-4. The time is "t17" and is 13ns max. Best Regards, Ken Crocker - Principal Engineer Ken Crocker Consulting paw wrote: > All, > > I am hoping that the experts on our list can help with > this. > > - We are using AMCC's 5933 PCI controller for an appl. > > - In regards to AMCC's "Add-On Bus" timing: there is a > signal named > "PTADR#" that is used to signal to the controller to > drive an address > onto the muxed address/data lines. I have not been able > to find a spec > on this operation. e.g. "the address will show up on the > DQ[] lines a > maximum of x nS after the falling edge of PTADR#" Any > help would be > greatly appreciated. Thanks. --paw > > Univ of Wisconsin > Space Science & Engineering Center > Republic of Madison, WI, USA
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