PCI-X sequences

["Francois Barlow" <fbarlow@matrox.com>]

Hi PCI-X experts,

Reading the new release of the PCI-X errata document (rev Z) revealed to me
that a bridge is not permitted to change the byte count of a memory write
transaction sequence (clarification C-35; new section 8.4.6 "Forwarding
memory write transactions").

In the PCI-X specification (rev 1.0), section 2.11.1.1, page 88, last
paragraph: "If the initiator intends to disconnect a transaction on the
first ADB, and the width of the bus is such that the starting address is
less than four data phases from the ADB, the initiator must adjust the byte
count to terminate the transaction on the ADB".

It seems that this sentence does not apply to PCI-X bridges anymore, and I
can't figure out why it could be a problem to do so.

In the following context:

- A transaction crosses a PCI-X to PCI-X bridge
- the transaction is a new sequence that begins less than four data phases
from the first ADB, and the byte count is such that the transaction ends
over the first ADB
- only one ADB of buffer space is still available to store the new
transaction
- the PCI-X bridge disconnect the transaction on the first ADB (no more
buffer space)
- The data for the next ADB is still not present in the buffer, and the
other bridge interface is ready to forward this first transaction sequence
on the bus

Under these conditions, what are the consequences to break a single sequence
in two sequences (using the same sequence IDs and TAGs), since both of them
are consecutives and would remain in the same order anyway?

Why can't we just adjust the byte count to end the transaction on the first
ADB?  When the data of the next ADB will become available in the bridge
buffer, that portion of the original transaction will be resumed using the
adjusted byte count, the same sequence ID and the same TAG.  On the PCI-X
target point of view, it is seen as two consecutive transactions using the
same sequence ID and the same TAG; which is allowed when the transactions
are posted one after the other.

Thanks a lot,

François.

+----------------------------------+
| François Barlow                  |
| ASIC Design Leader               |
| Matrox Electronic Systems        |
| http:\\www.matrox.com            |
| V:(514)685-7230 x2280            |
| F:(514)822-6110                  |
| mail: fbarlow@matrox.com         |
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