RE: IDSEL assignment

[Lame Brooks-G14738 <brooks.lame@motorola.com>]

I think Wilson was talking about the central resource.  For a "typical PC,"
I think the answer should be "the latter."  The three different mfgs of
Intel Arch chipsets that I've looked at, all follow the implementation note
in section 3.2.2.3.5 of PCI 2.2 (sec 3.7.4 in PCI 2.1).
-- BrooksL

> -----Original Message-----
> From: Michael Richardson [mailto:mcr@solidum.com]
> Sent: Wednesday, 31 May, 2000 10:18
> To: pci-sig@znyx.com
> Subject: Re: IDSEL assignment 
> 
> 
> 
> >>>>> "Wilson" == Wilson Leung <wleung@arkon.bc.ca> writes:
>     Wilson> How does a typical PC route the IDSEL pins?  Does 
> it have a dedicated IDSEL
>     Wilson> pin (possibly from a bridge device) for each PCI 
> agent/slot? Or if the AD
>     Wilson> lines
>     Wilson> are used and tied to the IDSEL signals of each agent?
> 
>   The former. The bridge's control IDSEL. 
> 
>   The host bridge has some magic to control IDSEL, the PCI/PCI bridges
> generate it in response to type 1 config cycles, generating a 
> type 0 on
> the secondary bus. 
> 
>   The host bridge's magic depends on the CPU, etc. but Intel 
> host bridges
> use I/O port 0x0C0 or some such.
> 
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