RE: Level / edge interrupts

["Ingraham, Andrew" <Andrew.Ingraham@compaq.com>]

>PCI IRQ = level sensitive, perfect
>PCI IRQ = edge sensitive, system failure

Possible scenario: If interrupts are shared (wire-ORed), and a second
interrupt comes in before the first one is serviced, then there is only one
edge.  The INTx# line stays low after clearing the first interrupt.  If the
system is edge sensitive, it would never notice that the second interrupt
had occurred.  Even worse, it would be blind to any more interrupts on that
line!

PCI interrupts are defined to be level sensitive.  After the first one is
serviced and cleared, INTx# would have remained asserted and the system
should check for another until INTx# becomes de-asserted.