Re: PCI slow slew rate cause failure

[yang.can.mei@philips.com]

John,

Not sure about the detailed failure cause, but in general, the slew rate does affect the signal quality. Slow slew rate means longer propagation delay, that causes the output of CMOS cirucuit longer rising/falling timing delay. So even the setup time and 
hold time are ok before going into PCI device internal logic, after some logics, the setup time and hold time may be out of the  requirement of those later logic circuits.


Paul Yang C.M.
Philips Semiconductors, Asia Product Innovation Centre






John@quantatw.com on 12/06/2000 16:30:28
To:	pci-sig@znyx.com@SMTP
cc:	 
Subject:	PCI slow slew rate cause failure
Classification:	Restricted
Dear all PCI members,

One question regarding the slew rate of PCI 33Mhz signal.

One of our systems  fail PCI bus test.  
After measurement, we find that the PCI signals has slow slew rate. The PCI
spec. require the slew rate is within 1v/ns to 4v/ns at 0.2Vcc - 0.6Vcc
load. The PCI signals we have has 0.8v/ns.
However, the setup time and hold time do meet PCI spec, 7ns and 0ns
respectively.
  
My question is why the slow slew rate will cause the failure. Why PCI spec.
need to limit the
slew rate? Isn't the requirement of  setup time, hold time and signal
quality enough?

Thank you for your helps in advance.

Best regards,

John Lin
SI Engineer 
Quanta Computer Inc.,Taiwan, R.O.C.
Email: John@quantatw.com
Tel: 886+3+3979000 ext. 5183

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