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Split Completion Issue
I have a BAR which requests for 4k address space. But the device
connected to this BAR can handle only 8bytes read or 8 bytes write.
In the case of write I do a Single Dataphase Disconnect and forward the
cycle to the device.
In the case of a read I signal a Split Response, but I have no way of
the initiator that I can handle only 8bytes of data and no more.
So if an initiator issues a read request with more than 8 bytes, say it
asked for 16bytes at a 64-bit aligned address, I respond with Split
Response. In the
Split Completion cycle I transfer 8 bytes (fetched from the device) only. I
by setting BCM bit and changing the bytecount field to 8 bytes in the
attribute phase of the Split Completion cycle. For the remaining bytecount
I do a Split Completion Message cycle with the overflow information.
My Question :
When I transfer the 8 bytes with Split Completion cycle, can I set
the BCM bit and change the bytecount to 8 bytes even though it is
not to disconnect the transaction on the first ADB ??
The PCI-X specification Ver1.0 has not specified the completer for a
Split Completion cycle setting the BCM bit for bytecount overflow case.
It specifies for disconnection on the first ADB only.
- SriKiran Dravida.