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wait states

To: <pci-sig@znyx.com>
Subject: wait states
From: "Daniel DeConinck" <daniel.deconinck@sympatico.ca>
Date: Wed, 14 Jun 2000 19:29:03 -0400
Sender: owner-reflector@www.pcisig.com

Hello,

How many wait states may a target insert during a read and during a write ?

In a wintel PCI enviroment, I uderstand that writes or read are not burst. Which is it ?

Also, what is the typical burst length? I heard it was 8 or 16 data phases.

Thanks

Dan

Follow-Ups:
- Re: wait states
  - From: Drew Eckhardt <drew@Poohsticks.ORG>

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