Power Sequencing and I/O Clamp

[dpannell@marvell.com]

I have a question about PCI Power Sequencing and I/O Clamping.  I have gone
through the entire PCI-SIG reflector archives as well as MANY vendor's
device specifications.  Here is what I have found:

It is clear to me that an I/O Clamp VREF is required in order to insure I/O
pads are 5 volt tolerant in a 5 volt environment and are 3.3 volt tolerant
in a 3.3 volt environment.  Basically this I/O Clamp VREF is connected to
the PCI VIO pins (which are either 3.3 volts or 5.0 volts depending upon
the environment of the system the card is plugged into).  Every PCI device
I looked at (from multiple vendors) appears to have this I/O Clamp
reference.  This includes devices like NICs and devices like CPU core
logic.  I did not check graphics since they are generally AGP and that's a
different story.

It is also clear in the PCI spec that the voltages on the PCI bus could be
sequenced in ANY order with no time limit specified.  How can these two
requirements work together?  If the VREF pin is connected to 3.3 volts and
it comes up seconds before the 5 volts the I/O pads would forward bias the
VREF diode and could cause damage!  This apparently has occurred in the
past because Intel now states in their most recent core logic data sheets
(in the 82806AA PCI 64 Hub - page 81) that if VREF is connected to 5 volts
is must power-up at the same time or before the 3.3 volts.  Power
sequencing is REQUIRED for their core logic!

In reality I think power sequencing has ALWAYS been required for the
semiconductor devices even if the PCI spec didn't require it.

Can you, the PCI-SIG community, confirm this (i.e., that in reality all
motherboards sequence their power or apply it simultaneously)?  If power
sequencing does not occur in motherboards how do these devices that use the
I/O Clamp VREF survive?  Is there an problem with the PCI spec here?

I appreciate your enlightenment on this subject!
--Don Pannell
Marvell Semiconductor