Calling all host bridge designers .....

[Alan Deikman <Alan.Deikman@znyx.com>]

Hello everyone,

I'm currently working on a white paper, and can can
use some help on this subject.  Out of the various
high-performance host-to-PCI bridge designs out there,
which ones actually (attempt to) optimize host CPU
access to the PCI bus?

For example,

   1. If I do multiple writes to the PCI bus, are
      those writes posted and combined into a burst
      on the PCI bus?
   2. If I do a read, what are the facilities for
      pre-fectch, so that subsequent sequential
      reads don't require another PCI transaction?

And anything else?  I am mostly interested in the
more popular bridge designs for Pentium, PPC, SPARC.
Anyone care to step up and brag about their design
a little?  (And a hyperlink to a PDF datasheet might
be nice as well.)

Much thanks.
---------------------------------------------------------------------
ZNYX Networks - Alan.Deikman@znyx.com - 510 249 0800 FAX 603 843 5867