Hello Alan--
I am not aware of any intelligent pci bridges, though my work has been limited to pci-to-pci bridging. I have seen examples of graphics controller ASICs which FIFO the write data bound from pci to gfx memory in which intelligent processing of queued data was possible. For example, when the FIFO was 3/4 full, an independent processor with a 3rd port to the FIFO memory [2nd read and write port] would attempt to combine write packets which themselves not necessarily being contiguous, contained contiguous destination addresses. If it could perform at least a 2:1 compression [2 packets to 1 due to contiguous destination addresses], then the FIFO contents would be edited to delete the packets it could cover by editing the one with the lowest address.
This process is complex, as you have possibly imagined, it requires a linked-list approach to FIFO'd data. In an embedded microprogrammable controller this is less difficult, though the overhead is not easily justifiable. With state-machines, this procedure would be a design nightmare. In this case, the only reason why this overhead was [theoretically] justified, was only in part due to the likelihood of an overrun on the FIFO; the primary justification was to allow a single-word "burst" to be the common mode of access, allowing a relatively simple interface for a dedicated process [i.e. allow random access to gfx memory to the granularity of a single word, given that the processing task could not look ahead to improve the access efficiency -- that burden was placed on the gfx controller].
Regards,
Ivan
-----Original Message-----
From: Alan Deikman [mailto:Alan.Deikman@znyx.com]
Sent: Thursday, June 22, 2000 9:51 AM
To: pci-sig@znyx.com
Subject: Calling all host bridge designers .....
Hello everyone,
I'm currently working on a white paper, and can can
use some help on this subject. Out of the various
high-performance host-to-PCI bridge designs out there,
which ones actually (attempt to) optimize host CPU
access to the PCI bus?
For example,
1. If I do multiple writes to the PCI bus, are
those writes posted and combined into a burst
on the PCI bus?
2. If I do a read, what are the facilities for
pre-fectch, so that subsequent sequential
reads don't require another PCI transaction?
And anything else? I am mostly interested in the
more popular bridge designs for Pentium, PPC, SPARC.
Anyone care to step up and brag about their design
a little? (And a hyperlink to a PDF datasheet might
be nice as well.)
Much thanks.
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