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RE: devices not seen, fpgas not getting the clock
VMETRO see this problem when plugging in Bus Analyzers quite often since
they are commonly transparent to the system BIOS.
To turn clocks back on I reset bit[3:2] of the Secondary Clock Control
Register. This registers
resides in the configuration space of the 21150 Bridge Chip at an offset of
x68. Check out page 130-131 of the following pdf from Intel. I set this
register to a value of 0x3f00.
In my Intel L440Gx+ motherboard this device has an VendorID = 0x1011 and a
DeviceId = 0x0023.
Follow the below URL and on page 131 you will see the slot 0 and slot 1
registers where the clock is being set to either on or off.
http://developer.intel.com/design/bridge/datashts/27810601.pdf
Leif Erik Laerum Ph: (281) 584 0728
VMETRO, Inc. Fax: (281) 584 9034
1880 Dairy Ashford, Suite 535 Efax: (413) 480-6440
Houston, TX, 77077 http://www.vmetro.com
> -----Original Message-----
> From: Olaf Birkeland [mailto:olaf@midten.fast.no]
> Sent: Wednesday, June 28, 2000 1:42 PM
> To: Marco Brambilla (Wireline)
> Cc: pci-sig@znyx.com
> Subject: Re: devices not seen, fpgas not getting the clock
>
>
> This is probably for devices that are behind a DEC/Intel/TI 2115x type
> PCI/PCI bridge. These bridges can stop individual clocks by register
> settings. You can tweak the PCI bridge register yourself, but for
> getting you protoype board up running it would probably be sufficient to
> move it to one of the PCI slots that are on the primary PCI bus, *before*
> the PCI/PCI bridge.
>
> Regards,
> - Olaf
>
> On Wed, 28 Jun 2000, Marco Brambilla (Wireline) wrote:
>
> > Hi all,
> >
> > As someone else on the list, I too had some issues with clock not seen
> > by fpgas.
> >
> > In our case we have many HP PCs which are working fine.
> > In only one PC (a P3 500) we saw that during the initial boot phase the
> > clock is present on all 3 PCI slots on the motherboard.
> >
> > After some seconds (5 to 30) the clock remains good on populated slots,
> > while it is removed from empty slots.
> > At least this is what our lab people told me.
> >
> > The PC is thus fully functional, but we have a development board on
> > which our chip is implemented in fpga.
> > For debugging reasons we cannot program the FPGA from the external
> > memory, but from the jtag cable.
> > This means that our board can never be seen by the motherboard, because
> > at startup it was not operating, so the clock is removed from the slot.
> >
> > Has anyone ever heard of such a behaviour ?
> > Is this "clock removing" feature really present ? (and can it be
> > disabled) ?
> >
> > Thanks for any advice.
> >
> > Marco Brambilla
> >
> > --
> > --------------------------------------------------
> > Marco BRAMBILLA
> >
> > STMicroelectronics
> > Via C. Olivetti, 2
> > 20041 Agrate Brianza (MI)
> > ITALY
> >
> > TPA - Wireline Communications Division
> > tel : +39 039 603.5064 (ST Agrate - TINA 050)
> > tel : +33 (0)4 7658.5063 (ST Meylan - TINA 041)
> > fax : +39 039 603.5060
> > mailto:marco-tpa.brambilla@st.com
> > --------------------------------------------------
> >
> >
>
>